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4-mbit (256k x 16) static ram cy62147ev30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05440 rev. *e revised may 6, 2007 features ? very high speed: 45 ns ? temperature ranges ? industrial: ?40c to +85c ? automotive-a: ?40c to +85c ? automotive-e: ?40c to +125c ? wide voltage range: 2.20v?3.60v ? pin compatible with cy62147dv30 ? ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a (industrial) ? ultra low active power ? typical active current: 2 ma @ f = 1 mhz ? easy memory expansion with ce and oe features ? automatic power down when deselected ? cmos for optimum speed and power ? offered in pb-free 48-ball vfbga and 44-pin tsopii packages ? byte power down feature functional description [1] the cy62147ev30 is a high performance cmos static ram organized as 256k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: ? deselected (ce high) ? outputs are disabled (oe high) ? both byte high enable and byte low enable are disabled (bhe , ble high) ? write operation is active (ce low and we low) to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. logic block diagram 256k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 bhe ble ce power down circuit note 1. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines. [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 2 of 12 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62147ev30ll ind?l/auto-a 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7 cy62147ev30ll auto-e 2.2 3.0 3.6 55 ns 2 3 15 25 1 20 notes 2. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25. 3. nc pins are not connected on the die. 4. pins h1, g2, and h6 in the bga package are address expansion pins for 8 mb, 16 mb, and 32 mb, respectively. pin configurations the figure that follows show the 48-ball vfbga and 44-pin tsop ii pinouts. [3, 4] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 a 17 48-ball vfbga 44-pin tsop ii top view top view we a 11 a 10 a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe a 7 io 0 bhe nc a 2 a 1 ble io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss a 17 [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 3 of 12 maximum ratings exceeding the maximum ratings may shorten the battery life of the device. user guidelines are not tested. storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied .......... .............. .............. ..... ?55c to + 125c supply voltage to ground potential ...................... ...... ?0.3v to + 3.9v (v ccmax + 0.3v) dc voltage applied to outputs in high-z state [5, 6] ................?0.3v to 3.9v (v ccmax + 0.3v) dc input voltage [5, 6] ............?0.3v to 3.9v (v ccmax + 0.3v) output current into outputs (low) ............................ 20 ma static discharge voltage ........ ........... ............ ........... >2001v (mil-std-883, method 3015) latch up current...................................................... >200 ma operating range device range ambient temperature v cc [7] cy62147ev30ll ind?l/auto-a ?40c to +85c 2.2v to 3.6v auto-e ?40c to +125c electrical characteristics over the operating range parameter description test conditions 45 ns (ind?l/auto-a) 55 ns (auto-e) unit min typ [2] max min typ [2] max v oh output high voltage i oh = ?0.1 ma 2.0 2.0 v i oh = ?1.0 ma, v cc > 2.70v 2.4 2.4 v v ol output low voltage i ol = 0.1 ma 0.4 0.4 v i ol = 2.1 ma, v cc = 2.70v 0.4 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3 1.8 v cc + 0.3 v v cc = 2.7v to 3.6v 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?4 +4 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?4 +4 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels 15 20 15 25 ma f = 1 mhz 2 2.5 2 3 i sb1 automatic ce power down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v, v in < 0.2v f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = 3.60v 17 120 a i sb2 [8] automatic ce power down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 17 120 a capacitance for all packages. [9] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il(min) = ?2.0v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.75v for pulse durations less than 20 ns. 7. full device ac operation assumes a minimum of 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 8. only chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 9. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 4 of 12 thermal resistance [9] parameter description test conditions vfbga package tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 c/w jc thermal resistance (junction to case) 10 13 c/w ac test loads and waveforms figure 1. ac test load and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics over the operating range parameter description conditions min typ [2] max unit v dr v cc for data retention 1.5 v i ccdr [8] data retention current v cc = 1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v ind?l/auto-a 0.8 7 a auto-e 12 t cdr [9] chip deselect to data retention time 0 ns t r [10] operation recovery time t rc ns data retention waveform [11] figure 2. data retention waveform v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce or bhe .ble notes 10. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 11. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble . [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 5 of 12 switching characteristics over the operating range [12, 13] parameter description 45 ns (ind?l/auto-a) 55 ns (auto-e) unit min max min max read cycle t rc read cycle time 45 55 ns t aa address to data valid 45 55 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 45 55 ns t doe oe low to data valid 22 25 ns t lzoe oe low to low z [14] 55ns t hzoe oe high to high z [14, 15] 18 20 ns t lzce ce low to low z [14] 10 10 ns t hzce ce high to high z [14, 15] 18 20 ns t pu ce low to power up 0 0 ns t pd ce high to power down 45 55 ns t dbe ble /bhe low to data valid 45 55 ns t lzbe ble /bhe low to low z [14] 10 10 ns t hzbe ble /bhe high to high z [14, 15] 18 20 ns write cycle [16] t wc write cycle time 45 55 ns t sce ce low to write end 35 40 ns t aw address setup to write end 35 40 ns t ha address hold from write end 0 0 ns t sa address setup to write start 0 0 ns t pwe we pulse width 35 40 ns t bw ble /bhe low to write end 35 40 ns t sd data setup to write end 25 25 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [14, 15] 18 20 ns t lzwe we high to low-z [14] 10 10 ns notes 12. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1v/ns) or less, ti ming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 13. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 14. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 15. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble , or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of t he signal that terminates the write. [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 6 of 12 switching waveforms read cycle no. 1 (address transition controlled) [17, 18] figure 3. read cycle no. 1 read cycle no. 2 (oe controlled) [18, 19] figure 4. read cycle no. 2 previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 17. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 18. we is high for read cycle. 19. address valid before or similar to ce and bhe , ble transition low. [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 7 of 12 write cycle no. 1 (we controlled) [16, 20, 21] figure 5. write cycle no. 1 write cycle no. 2 (ce controlled) [16, 20, 21] figure 6. write cycle no. 2 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 22 t bw t sce data io address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data io oe bhe /ble note 22 notes 20. data io is high impedance if oe = v ih . 21. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 22. during this period, the ios are in output state. do not apply input signals. [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 8 of 12 write cycle no. 3 (we controlled, oe low) [21] figure 7. write cycle no. 3 write cycle no. 4 (bhe /ble controlled, oe low) [21] figure 8. write cycle no. 4 switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 22 ce address we data io bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 22 data io address ce we bhe /ble [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 9 of 12 truth table ce we oe bhe ble ios mode power h x x x x high z deselect/power down standby (i sb ) l x x h h high z deselect/power down standby (i sb ) l h l l l data out (io 0 ?io 15 )read active (i cc ) lhlhldata out (io 0 ?io 7 ); io 8 ?io 15 in high z read active (i cc ) l h l l h data out (io 8 ?io 15 ); io 0 ?io 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (io 0 ?io 15 ) write active (i cc ) l l x h l data in (io 0 ?io 7 ); io 8 ?io 15 in high z write active (i cc ) l l x l h data in (io 8 ?io 15 ); io 0 ?io 7 in high z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 cy62147ev30ll-45bvi 51-85150 48-ball very fine pitch ball grid array industrial cy62147ev30ll-45bvxi 51-85150 48-ball very fine pitch ball grid array (pb-free) cy62147ev30ll-45zsxi 51-85087 44-pin thin small outline package ii (pb-free) 45 CY62147EV30LL-45BVXA 51-85150 48-ball very fine pitch ball grid array (pb-free) automotive-a 55 cy62147ev30ll-55zsxe 51-85087 44-pin thin small outline package ii (pb-free) automotive-e contact your local cypress sales repres entative for availability of these parts. [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 10 of 12 package diagrams figure 9. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 11 of 12 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 10. 44-pin tsop ii, 51-85087 mobl is a registered trademark, and more battery life is a tr ademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85087-*a [+] feedback [+] feedback
cy62147ev30 mobl ? document #: 38-05440 rev. *e page 12 of 12 document history page document title: cy62147ev30 mobl ? 4-mbit (256k x 16) static ram document number: 38-05440 rev. ecn no. issue date orig. of change description of change ** 201861 01/13/04 aju new data sheet *a 247009 see ecn syt changed from advanced information to preliminary moved product portfolio to page 2 changed vcc stabilization time in footnote #8 from 100 s to 200 s removed footnote #15(t lzbe ) from previous revision changed i ccdr from 2.0 a to 2.5 a changed typo in data retention characteristics(t r ) from 100 s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzbe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce and t bw from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to 18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin changed ordering information to include pb-free packages *b 414807 see ecn zsd changed from preliminary information to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35ns speed bin removed ?l? version of cy62147ev30 changed ball e3 from dnu to nc. removed redundant foot note on dnu. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max changed i sb1 and i sb2 typ values from 0.7 a to 1 a and max values from 2.5 a to 7 a. changed i ccdr from 2.5 a to 7 a. added i ccdr typical value. changed ac test load capacitance from 50 pf to 30 pf on page #4. changed t lzoe from 3 ns to 5 ns changed t lzce , t lzbe and t lzwe from 6 ns to 10 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns. changed t sd from 22 ns to 25 ns. updated the package diagram 48-pin vfbga from *b to *d updated the ordering information table and replaced the package name column with package diagram. *c 464503 see ecn nxr included automotive range in product offering updated the ordering information *d 925501 see ecn vkn added preliminary automotive-a information added footnote #9 related to i sb2 and i ccdr added footnote #14 related ac timing parameters *e 1045701 see ecn vkn converted automotive-a and automotive -e specs from preliminary to final [+] feedback [+] feedback

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